1. Field of the Invention
This invention relates to processor design simulation and particularly to a method and apparatus of handling instruction rejects, partial rejects, stalls and branch wrong in a simulation model.
2. Description of Background
In today's complex processor designs, simulation often breaks into small units for easy verification and better chances of finding more bugs at the unit levels. At unit level simulations, various monitors will be in place to monitor various functions and signals depending on the functions at each unit. In the last decade IBM has used various hierarchical verification approaches using simulation engines at the unit and chip level, such as using the SIMAPI user interface for simulation at macro levels, and commercially available VHDL event simulators have been used, such as the cycle simulator TEXSIM and ZFS to perform cycle simulation for the S/390 machines. This work has continued with multi-unit level simulations and multiple chip, system level for early validation of a processor design prior to completing the design in a hardware definition language (HDL). However, simulation requires a lot of staffing for verification, and improvements are desirable, especially those able to be applied to architectures which can include reduced-instruction-set computers and traditional CISC architectures such as the IBM System z machines and Intel architectures.